I designed and developed a configureable 4-channel DDR LVDS Serialized AXI FPGA interface in SystemVerilog (up to 250MHz) for time-digital-converter application on an Xilinx Zynq SoC. The TDC was interfaced to the FPGA SoM that I designed. In addition to the FPGA interface, I also developed the kernel and user-space drivers for accessing/debugging the interface and TDC from the SoC Linux environment. To leverage full speed data transfers of the FPGA interface I designed, a AXI to USB 3.0 SuperSpeed interface was designed to stream the serialized TDC datastream to a downstream computer.
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